Attached is a CPU diagram for a two-bus architecture and a function table for its ALU. It differs from the 3-bus architecture discussed in class in several ways. Most notably, there is no direct connection between the two buses, other than through an ALU function. Also, there are separate Read and Write lines for memory, latches to hold the ALU inputs, and two data registers.1) Give the sequence of control signals necessary to implement the fetch cycle already answered this oneonly need the answer for question 22) Once the instruction has been fetched, give sequence of control signals required to implement the instruction SUB D0, D1 which is defined in RTL as [D0] ? [D0] - [D1]
This question was answered on: Sep 21, 2023
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