1. An example of language translation would be: a) Windows NT b) a C++ compiler c) Raid level 0 d) ALU e) Data flow2. A virtual machine is a hypothetical computer which: a) can never be implemented b) has a machine language which is not well defined c) has a machine language which can be translated or interpreted d) is the basic idea behind the Pentium and Core Series e) contains a BLU3. Hardware and software: a) are logically different b) cannot be converted from one to another c) are made up of logic gates d) are logically equivalent e) are not needed in a virtual machine4. Ada King, Countess of Lovelace was: a) the inventor of the Analytical Engine b) the inventor of operating systems c) the inventor of logic gates d) the first programmer e) the inventor of C++5. The von Neumann architecture: a) is still used today b) in not used today c) was implemented in first computer designed by Eckert d) did not used the concept of stored program e) had hardwired programs6. VLSI : a) was used in the first computer b) is predicted by Nathan's law c) is the basis for the current generation of computers d) stands for Vertical Length Scsi Integration e) is no longer important in the next generation of computer systems7. The Program Counter register: a) is located in the Data Path b) points to the next instruction c) holds the next instruction d) receives the result of the ALU computation e) is always incremented by 18. The sequence of steps that a CPU performs in the execution of a program is called: a) fetch-jump-decode b) increment-jump-decode c) fetch-execute-decode d) fetch-decode-increment e) fetch-decode-execute9. RISC stands for: a) Reduced Interpretation Set Computer b) Restricted Instruction Set Computer c) Reduced Instruction Set Computer d) Redundancy Interpretation Set Computer e) Reduced Iteration Set Computer10. Which is not a general design goal of RISC computers: a) instructions should be easy to decode b) maximize rate at which instructions are issued c) direct hardware execution of instructions d) minimize number of registers on the chip e) maximize pipelining11. Pipelining improves processor speed because: a) it has more stages than a typical processor design b) allows all of the hardware to be busy at the same time c) has more transistors d) allows stages to interconnect in a non-linear way e) lets the ALU compute efficiently12. If a pipeline has 10 stages, and each stage executes its task in 2 nanoseconds (ns.), how often is an instruction completed (after the pipeline is filled): a) 1 ns. b) 2 ns. c) 4 ns. d) 8 ns. e) 10 ns.13. A general problem of using two simultaneous pipelines is: a) uses too much hardware b) too slow c) instructions may have conflicting dependencies d) too many registers on the chip cause instruction overlapping e) cannot have more that 1 write-back stage14. Array processors general use: a) only one CPU with multiple stages b) many processors connected in an irregular fashion c) many processors connected together with one bus d) many processors connected in a geometric pattern e) one CPU connected via the Internet15. A multi-processor configuration uses: a) several different buses to connect the processors b) several similar buses to connect the processors c) a single bus to connect the processors d) one CPU connected by the USB to the hard drive e) local memory to connect the CPUs16. To minimize bus conflicts in a multi-processor computer, the following technique is generally used: a) add more shared memory to the CPUs b) add local memory to the CPUs c) increase bus width d) decrease bus width e) add more CPUs to the configuration17. Each memory location has a label called: a) a cell b) a bit ordering c) an address d) a binary coded decimal e) a variable length encoding18. Byte ordering: a) is not a problem in modern computers b) has been solved with specialized hardware c) can cause a problem if ASCII files are transferred between machines d) can cause a problem if binary files are exchanges between CPUs e) is not a problem between a Pentium and a Sparc processor19. Hamming codes are used for: a) just error detection b) error retransmission c) error detection and correction d) computing parity of a word e) minimizing word transmission length20. The basic idea behind Hamming codes: a) is to use a simple Parity bit to compute the code for the complete word b) is to use two Parity bits for each byte c) is to break up the word into non-overlapping bitsets each with a Parity bit d) is to break up the word into overlapping bitsets each with a Parity bit e) is to scramble the word so that it is immune to noise21. Hamming codes are more efficient as: a) the word length decreases b) the word length increases c) the byte ordering changes d) bus width increases e) the USB gets faster22. Cache memory: a) is used to decrease bus bandwidth b) is used as a PCI bridge c) is as large as main memory d) works because of the principle of locality e) is no longer needing in Pentium CPUs23. In general, in the memory hierarchy, memory that is faster: a) is more expensive b) is less expensive c) more of it is placed in the CPU d) more of it is placed on a CD-ROM e) is uniform24. RAID is used: a) as a memory speed-up mechanism b) as a tape backup policy c) as a safer way to store data on physical disks d) as a way to compute checksums e) to decrease the number of physical disks in a system25. Modems transfer data: a) directly over the Internet b) using binary signaling c) over phone lines using direct binary signals d) over phone lines using some modulation technique e) over a system bus using amplitude modulation
This question was answered on: Sep 21, 2023
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